Integrated circuits (ICs) typically include a plurality of semiconductor devices and interconnect wiring. Networks of metal interconnect wiring are often used to connect the semiconductor devices from the semiconductor portion of the substrate. Multiple levels of metal interconnect wiring form a plurality of metallization layers above the semiconductor portion of the substrate and are connected together to form a back-end-of-the-line (“BEOL”) interconnect structure. Within such a structure, metal lines run parallel to the substrate in the metallization layers and conductive vias run perpendicular to the substrate between the metallization layers to interconnect the metal lines.
High performance of contemporary ICs may be achieved using a highly conductive metal, such as copper, as the interconnect metal of the BEOL interconnect structure, which also employs a low dielectric constant (low-k) dielectric material as an interlevel dielectric (ILD) layer or layers. By “low k,” it is meant that the dielectric constant of a particular dielectric material is less than that of silicon dioxide. Typically, the low-k properties of the low-k dielectric material are established by incorporating porosity (e.g. air) into a dielectric material such as silicon dioxide to form a porous dielectric material.
Conventional fabrication of BEOL interconnect structures include forming an ILD layer of, for example, a porous dielectric material overlying a semiconductor substrate. To protect the ILD layer, a cap layer is deposited overlying the ILD layer. The cap layer is typically a layer of non-porous, dense material such as SiON or the like. A hard mask layer is then deposited and patterned overlying the cap layer. Using the patterned hard mask layer as an etch mask, via-holes and metal line trenches are etched through the cap layer into the ILD layer. The via-holes and metal line trenches are then filled with a conductive metal to form the conductive vias and metal lines that form part of the BEOL interconnect structure. Unfortunately, during the etching process prior to the conductive metal fill, undercuts and/or bowing can occur underneath the cap layer along the sidewalls of the ILD layer that define the via-holes and/or metal line trenches because the lateral etch rate of the much denser, non-porous cap layer is typically substantially less (e.g., slower lateral etch rate) than the lateral etch rate of the relatively porous ILD layer. As such, the ILD layer etches more readily in a lateral direction than the cap layer resulting in portions of the cap layer overhanging the sidewalls of the ILD layer. These undercuts and/or bowing conditions can be difficult to fill with a conductive metal and voids can form in the BEOL interconnect structure due to incomplete metal filling of the via-holes and metal line trenches. These voids are undesirable and can create a number of issues including increasing the resistance of the BEOL interconnect structure.
Accordingly, it is desirable to provide methods for fabricating integrated circuits including forming a back-end-of-the-line interconnect structure while reducing, minimizing, or preventing the formation of voids in the interconnect structure. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.